I. Field of the Disclosure
The technology of the disclosure relates generally to metal-oxide semiconductor (MOS) field-effect transistors (MOSFETs), and particularly to MOSFETs used as programmable dipole switching devices, such as in memory cells.
II. Background
In modern computing systems, processors such as central processing units (CPUs) and digital signal processors (DSPs) process binary input signals based on a set of machine executable binary instructions and generate binary output signals as a result. To produce the expected results, processors must be able to accurately determine the state of an input signal (e.g., whether the input signal represents a binary zero or a binary one). The determinations are usually based on detecting a voltage level of the input signal and are carried out by logic gates. These logic gates may consist of various metal-oxide semiconductor (MOS) field-effect transistors (MOSFETs) arranged in a manner as to provide the desired logic operation. A MOSFET may be an n-channel MOSFET (nMOSFET) or a p-channel MOSFET (pMOSFET) depending on substrate materials.
In this regard, FIG. 1 illustrates an exemplary nMOSFET 100 that may be included in a logic gate. The nMOSFET 100 includes a metal gate (MG) 102, an n-type source region 104, an n-type drain region 106, and a p-type substrate (P-sub) (body) 108. A dielectric layer/interface layer 110 (e.g., a high-K dielectric layer/interface layer) is disposed between the metal gate 102 and the body 108. The metal gate 102, the n-type source region 104, and the n-type drain region 106 are coupled to a gate (G) electrode 112, a source (S) electrode 114, and a drain (D) electrode 116, respectively.
A gate voltage (VG) 118 and a source voltage (VS) 120 provide a switching voltage (VGS) 122 that switches the nMOSFET 100 between an accumulation mode and an inversion mode. If the switching voltage (VGS) 122 is less than a threshold voltage (VT) of the nMOSFET 100, the nMOSFET 100 is in the accumulation mode or a depletion mode regardless of a drain voltage (VD) 124. When the nMOSFET 100 is in the accumulation or the depletion mode, a channel region 126 between the n-type source region 104 and the n-type drain region 106 becomes highly resistive. As a result, no electrical current flows between the n-type source region 104 and the n-type drain region 106. When the switching voltage (VGS) 122 is greater than or equal to the threshold voltage (VT) of the nMOSFET 100, the nMOSFET 100 switches into an inversion mode, and the channel region 126 becomes conductive. In the inversion mode, if a drain-to-source voltage (VDS) 128 is applied between the drain (D) electrode 108 and the source (S) electrode 106, electrons 130 are drawn to the n-type drain region 106 from the n-type source region 104, thus generating a switching electrical current (ID) 132 flowing from the n-type drain region 106 to the n-type source region 104.